#  Jeff Mock
#  2030 Gough
#  San Francisco, CA 94109
#  jeff@mock.com
#  (c) 2004-2006
# 
# 
#  $URL: https://www.mock.com/svn/pdev/trunk/sw/src/pnet.conf $
#  $Id: pnet.conf 859 2007-01-19 04:20:18Z jeff $
# 

# Sample pdev.conf file for testing
#

# include "boxes.conf"
[pdev]
# name  IP address  Beam    Subband sp  setup   file server
#
#b0a      pdev-111    0       0       0   gxa      tdevs0  
#b0a     pdev-126    0       0       0   gxa     pdevs0  
b0a     pdev-123    0       0       0   gxa     pdevs0  
# b0b     pdev-107    0       1       1   gxa     tdevs0

include "cal.conf"

# The signal processor ID and version number expected in the 
# FPGAs
#
[sp 02.02]

# These are registers defs for the signal processor.  A
#
#
[defs]
CREG_DEC_F                0
CREG_ROUND_EN             1
CREG_TUNE_L               2   
CREG_TUNE_M               3   
CREG_D1_COUNT_L           4
CREG_D1_COUNT_M           5
CREG_S2_COUNT_L           6
CREG_S2_COUNT_M           7
CREG_D2_COUNT_L           8 
CREG_D2_COUNT_M           9 
CREG_S3_COUNT_L           10 
CREG_S3_COUNT_M           11 
CREG_D3_COUNT_L           12 
CREG_D3_COUNT_M           13 
CREG_SHIFT_FIR            14 
CREG_GP_SEL               15 
CREG_ADC1_SEL             16 
CREG_ADC2_SEL             17 

[dump]
packet          0x0200000        # Size of each data packet
name            sasdr_world
filesize        20000000     # in 1kbyte blocks
byteswap        1           # 0-7
adcclk          140.
magic           0x01234567  # Magic number for SP1 files
dma             65536       # DMA size from FPGA on spectrometer
gpoe            0x8         # Enable output on GPIO pins
ppssel          0           # GP input for PPS, default is 0
ppsedge         1           # set to one to use posedge of pps (default)
ppsforce        0           # Force a fake PPS to start obs (default is 0)

[header]
CREG_DEC_F        
CREG_ROUND_EN        
CREG_TUNE_L             
CREG_TUNE_M             
CREG_D1_COUNT_L           
CREG_D1_COUNT_M           
CREG_S2_COUNT_L           
CREG_S2_COUNT_M           
CREG_D2_COUNT_L           
CREG_D2_COUNT_M           
CREG_S3_COUNT_L           
CREG_S3_COUNT_M           
CREG_D3_COUNT_L           
CREG_D3_COUNT_M           
CREG_SHIFT_FIR
CREG_GP_SEL             
CREG_ADC1_SEL           
CREG_ADC2_SEL 

[setup gxa]
CREG_DEC_F  1          # Decimation 1 = 35M, 2=20M, 3=10M, 4=5M, 5=2.5M, 6= 1M 
CREG_ROUND_EN   0      # 1 = convergent rounding, 0 = truncation 
CREG_TUNE_L  28087     # Set to 30 MHz = 920350135, 14043 MSB and 28087 LSB 
CREG_TUNE_M  14043     # Tune center frequency word = Fcenter*2^32/140    
CREG_D1_COUNT_L  17500 # Number of decimated samples to dump window1 LSB       
CREG_D1_COUNT_M  0     # Number of decimated samples to dump window1 MSB
CREG_S2_COUNT_L  21000 # Number of decimated samples start of window2 LSB       
CREG_S2_COUNT_M  0     # Number of decimated samples start of window2 MSB
CREG_D2_COUNT_L  63964 
CREG_D2_COUNT_M  1 
CREG_S3_COUNT_L  0          
CREG_S3_COUNT_M  0         
CREG_D3_COUNT_L  0          
CREG_D3_COUNT_M  0         
CREG_SHIFT_FIR   8     # Shift left fir output, 0=0, 1=1 etc. 
CREG_GP_SEL      0     # 0 = GP0 selected            
CREG_ADC1_SEL    0     # 0 = ADC0 selected ( transmitter)           
CREG_ADC2_SEL    1     # 1 = ADC1 selected ( receiver )