GALFA Spectrometer Board Jumper Settings
Jumper placement diagram (pdf)
Jumper listing
Jumper settings for cPCI operations
Jumper listing
Power
- J9: +1.5V regulator control
- Jumper 1 to 3 (m_dn) to set +1.5V regulator (U4)
output to -5% nominal (+1.425V)
- Jumper 2 to 4 (m_up) to set +1.5V regulator (U4)
output to +5% nominal (+1.575V)
- J10: +1.5V connection
- Jumper 1 to 3 to provide +1.5V to FPGAs from
switching regulator U4
- Jumper 2 to 4 to provide +1.5V to FPGAs from
switching regulator U4
- J21: +1.5V connection
- Jumper 1 to 3 to provide +1.5V to FPGAs from switching
regulator U4
- Jumper 2 to 4 to provide +1.5V to FPGAs from switching
regulator U4
- J11: +2.5V regulator control
- Jumper 1 to 3 (m_dn) to set +2.5V regulator (U6)
output to -5% nominal (+2.375V)
- Jumper 2 to 4 (m_up) to set +2.5V regulator (U6)
output to +5% nominal (+2.625V)
- J12: +2.5V connection
- Jumper 1 to 3 to provide +2.5V to FPGAs from DC switching
regulator U6
- Jumper 2 to 4 to provide +2.5V to FPGAs from DC switching
regulator U6
- J20: +2.5V connection
- Jumper 1 to 3 to provide +2.5V to FPGAs from switching
regulator U6
- Jumper 2 to 4 to provide +2.5V to FPGAs from switching
regulator U6
- J16: -3V connection
- Jumper 1 to 3 to provide -3V to ADCs from linear regulator U8
- Jumper 2 to 4 to provide -3V to ADCs from linear regulator U8
- J17: +3V connection
- Jumper 1 to 3 to provide +3V to ADCs from linear regulator U9
- Jumper 2 to 4 to provide +3V to ADCs from linear regulator U9
Clocking
- J2: Clock Source
- Jumper 1 to 3 (xtal) to use on-board crystal oscillator
in socket U1
- Jumper 2 to 4 (xtern) to use external clock received
through RJ45 J1
- J5: SYNC
- Jumper 1 to 3 to drive SYNC_OUT directly from SYNC_IN
- Jumper 2 to 4 to generate SYNC_OUT from 2V4000/2V6000 FPGA
- J6: XTRA
- Jumper 1 to 3 to drive XTRA_OUT directly from XTRA_IN
- Jumper 2 to 4 to generate XTRA_OUT from 2V4000/2V6000 FPGA
- J7: 1PPS
- Jumper 1 to 3 to drive 1PPS_OUT directly from 1PPS_IN
- Jumper 2 to 4 to generate 1PPS_OUT from 2V4000/2V6000 FPGA
- J8: CLK
- Jumper 1 to 3 to drive CLK_OUT directly from CLK_IN
- Jumper 2 to 4 to generate CLK_OUT from 2V4000/2V6000 FPGA
Compact PCI Interface
- J19: cPCI Interface Clock
- Jumper 1 to 2 to enable 66MHz interface
FPGA Configuration
- JP1: 2V4000/2V6000
- Jumper 1 to 2 to ground programming mode pin M0
- Jumper 3 to 4 to ground programming mode pin M1
- Jumper 5 to 6 to ground programming mode pin M2
- JP2: 2V1000
- Jumper 1 to 2 to ground programming mode pin M0
- Jumper 3 to 4 to ground programming mode pin M1
- Jumper 5 to 6 to ground programming mode pin M2
(From Xilinx Virtex-II Platform FPGA Handbook)
| Configuration Mode |
M2 |
M1 |
M0 |
| Master Serial |
0 |
0 |
0 |
| Slave Serial |
1 |
1 |
1 |
| Master SelectMAP |
0 |
1 |
1 |
| Slave SelectMAP |
1 |
1 |
0 |
| Boundary Scan |
1 |
0 |
1 |
Jumper settings for normal (cPCI) operations
Leave the following jumpers UNCAPPED:
- J5
- J6
- J7
- J8
- J9
- J11
- J19
- JP1
- Remove crystal oscillator from U1
INSTALL the following jumpers:
- J2, connect 2 to 4
- J10, 2 jumpers (1 to 3, 2 to 4)
- J21, 2 jumpers (1 to 3, 2 to 4)
- J12, 2 jumpers (1 to 3, 2 to 4)
- J20, 2 jumpers (1 to 3, 2 to 4)
- J16, 2 jumpers (1 to 3, 2 to 4)
- J17, 2 jumpers (1 to 3, 2 to 4)
- JP2, 3 jumpers (1 to 2, 3 to 4, 5 to 6)