Jeff Mock
        2030 Gough
        SF, CA 94109

        415 346-2829
        jeff@mock.com


Test design for XC2V1000 on Aaron's board.  This is a
simple PCI target for controlling the LEDs and loading 
Xilinx configuration into the XC2V6000. 

Pinout in UCF file is seutp for Aarons board.

There are two constraints files for 33MHz and 66MHz.  Select
the desired file in Makefile.defs.  This is 66MHz by default,
there are a couple of timing constraints that miss by abot 0.5ns,
so it will probably work okay at 66MHz...

You need the following tools:

        Xilinx ISE 6.1 sp3 (or better) for linux
        cver verilog simulator (free) (www.pagmatic-c.com/gpl-cver)
            At this writing I'm using version 1.10d
        gtkwave waveform viewer (free) (I use 1.2.99, I think newer versions
            have problems)

Make sure XILINX environment variable is set to correct path.

Typing "make" at the top level will synthesize the chip, place
and route, and generate a prom file for to burn in the xc18v04 
to download with xchecker.

The directories are as follows:

        src             All of the source files for the design
        sim             functional simulation
        build           FPGA synthesis, place and route, etc
        sim_r           post-route gate level sim
        v2_pci_64_66    64-bit/66MHz PCI core

The file src/Makefile.defs has some definitions that might
need to change for your local environment.


version 0.02    1/17/4
        Fixed up some minor Makefile dependencies
        Changed pinout to new mangled bitreversed PCI pinout

versiob 0.03    2/25/4
        Change loading to MSB first to match .bin file from
        bitgen for faster loading.