High Performance CMOS Correlator Chip

Product Specification
NASA SER8 for VLSI Systems Design
University of New Mexico, Albuquerque, NM 87106
(505)277-9700 FAX (505)277-9719

February 13, 1995

1    Features:

 

2    General Description:

The correlator chip accepts two data streams (Stream A and Stream B) at a maximum sample rate of 100 MHz. Samples from Stream A are successively delayed (in a 1024-stage internal shift register) and multiplied by the (undelayed) data from Stream B. Arithmetic is performed in 1024 individual multiplier/accumulators, operating in parallel. At the end of an integration period the data in the accumulators is parallel-loaded into 1024 output registers. New integration can begin immediately. The contents of the output registers can be shifted out at rates up to 20 MHz, via a 32-bit tri-stating output port.

Chip Block Diagram [100 Kb gif]

 

3    Functional Description:

3.1    Data Input

Both input streams (Stream A and Stream B) use two bits (A0,A1 and B0,Bl). Only three, of the four possible, data words are valid. These three words, designated +1,0,-l, correspond to input signals more positive than a voltage threshold, ci, a voltage threshold between and -, and a voltage threshold more negative than -, respectively.

B data and A data, which propagates down the internal shift register, are updated on each clock cycle in which the Shift Enable (SE) control signal is high.

 

3.2    Auxiliary Data Input

The chip has 2-input multiplexers on both Stream A and Stream B. When AUXINA is low) the correlator takes Stream A from the A0 and Al pins. When AUXINA is high , the correlator takes Stream A from the AUXA0 and AUXA1 pins. Stream B works in the same manner, using AUXINB, AUXB0 and AUXB1.

 

3.3    Data Cascading

Stream A and Stream B are output, after an extra delay for synchronization, as A0OUT, A1OUT, B0OUT and B1OUT. These pins can be tied to the A and B inputs of another chip, to form cascades with multiples of 1024 lags.

 

3.4    Control Cascading

To avoid high-speed global control signal distribution, control signals are passed through the chip, with an extra delay for synchronization. These control signal outputs are INTO, SEO and BLANKO.

 

3.5    Auxiliary Data Output

The four AUXIN signals are synchronized with unit delays and output as AUXA1O, AUXA0O, AUXB1O and AUXB0O. These outputs can be tied to the AUXIN pins of an adjacent chip in order to distribute data down and across a board. This mechanism avoids problems associated with high-speed data bus distribution.

 

3.6    Multipliers

The products of the two 3-level data words have three possible values: +1, 0, -l. These are biased up to 2, 1 and 0 to allow the accumulation of all positive values. The multiplier consists of a modulo-2 counter, with the counter overflow driving the input of a 32-bit asynchronous ripple counter. The maximum overflow rate is equal to the clock rate and occurs when the biased product is always 2.

The chip operates as a 2-level correlator when it is supplied with data that contains no zeros (equivalent to setting the voltage threshold, , to zero).

Table 1 shows the representation of input data.

Table 1: Input Data Representation

 Bit 1

 Bit 0

 Value

0

0

0

0

1

1

1

0

-1

1

1

Illegal

 

3.7    Blanking

If BLANK is brought and held high during an integration period the overflow counters are isolated from the accumulators, effectively ignoring input data during the blanking period. Accumulation begins again when BLANK is brought and held low.

 

3.8    Initialization

The chip is initialized by completing a least one integration period.

 

3.9    Integration

Integration periods are framed by the INT control signal. At the end of the integration period INT is brought and held low. Upon bringing INT low the overflow counters will be isolated from the multipliers and allowed to settle. The contents of the overflow counters will then be dumped into the output registers. Data will be available for reading 30 clock cycles after INT is brought low, at which time a new integration can begin, by bringing, and holding, INT high. Integration periods can be as short as 10 clock cycles, however, any integrated data not read out will be overwritten.

 

3.10    Data Readout

Data reads are under the control of the CHIP ENABLE (CE) and READ pins. When CE is high, data will be appear on the 32-bit output bus (D0-D31) on the rising edge of READ. 1024 successive strobes of READ are required to output data from the chip. Data appears in order of increasing lags, with lag 0 appearing first. If all 1024 lags are not read out before the current integration period ends data from the unread lags will be overwritten. The maximum output frequency is 20 MHz for a maximum data rate of 80 MBytes/second.

 

3.11    Double Nyquist Sampling

Holding the control DUBL high will introduce an additional delay element (dummy lag) between each delay element of the shift register of Data Stream A. The resulting lagged products are thus accumulated at a clock period that is half the time separation between lags. Using this option provides an effective increase in signal-to-noise (by reducing quantization noise) but halves the maximum bandwidth.

 

3.12    Test Mode

Test mode provides a method for checking the operation of the 32-bit overflow counters. Test mode is entered by bringing and holding TEST high, while in an integration period. Test mode breaks the overflow counters into four 8-bit counters, the inputs to which are the overflow bit of the accumulator in each lag. An appropriate input pattern must be applied to the A and B buses during test mode operation. Access to the counters is the same as during normal operation.

 

3.13    Sample Counter

The number of non-blanked samples is provided by an internal counter which can be accessed in the same manner as normal lag output data. The counter is attached to the end of the output shift register and can be read like a 1025th lag. The counter does not need to be accessed unless desired.

 

4    Pin Out Diagram

 

Figure 2: 84 PIN CLCC/PLCC

 

5    Signal Descriptions

 

Signal Descriptions

Pin No.

Name

Function

1

 DO30 Bit 30 of the output bus.

2

 DO31 Bit 31 of the output bus. (Most significant bit)

3

 ACCR Accumulator Reset. (Active Low)

4

 DUBL Oversampling Enable. Enables oversampling

5

 TEST Test mode pin.

8

 AUXA0 Bit 0 of the auxiliary delayed signal.

9

 A0 Bit 0 of the delay signal.

10

 AUXA1 Bit 1 of the auxiliary delay signal.

11

 A1 Bit 1 of the delay signal.

14

 AUXINA A input port mux control.

15

 TVDD Positive power supply for TTL buffers. Normally +5V

16

 TVSS Supply reference for TTL buffers. Ground.

17

 CE Enables data read operations

18

 READ Output data appears on rising edge, when chip enabled.

19

 BLANK Blanking Enable. Enables blanking.

20

 SE Shift Enable. Enables shifting of delay line.

21

 INT Correlation period framing signal.

22

 CLOCK System clock.

25

 AUXINB B input port mux control.

26

 B1 Bit 1 of undelayed signal.

27

 AUXB1 Bit of the auxillary undelayed signal.

28

 B0 Bit 0 of undelayed signal.

29

 AUXB0 Bit 0 of the auxiliary undelayed signal.

30

 DO0 Bit 0 of the output bus. (Least significant bit)

33

 DO1 Bit 1 of the output bus.

34

 DO2 Bit 2 of the output bus.

35

 A1OUT Bit 1 of the delayed signal output.

36

 AUXA1O Bit 1 of the auxiliary delayed signal output.

39

 A0OUT Bit 0 of the delayed signal output.

40

 AUXA0O Bit 0 of the auxiliary delayed signal output.

41

 DO3 Bit 3 of the output bus.

42

 DO4 Bit 4 of the output bus.

43

 DO5 Bit 5 of the output bus.

44

 DO6 Bit 6 of the output bus.

45

 DO7 Bit 7 of the output bus.

46

 DO8 Bit 8 of the output bus.

47

 DO9 Bit 9 of the output bus.

Signal Descriptions continued
50 DO10 Bit 10 of the output bus.

51

 DO11 Bit 11 of the output bus.

52

 DO12 Bit 12 of the output bus.

53

 DO13 Bit 13 of the output bus.

56

 DO14 Bit 14 of the output bus.

57

 DO15 Bit 15 of the output bus.

58

 DO16 Bit 16 of the output bus.

59

 AUXB0O Bit 0 of the auxiliary undelayed signal o/p

60

 B0OUT Bit 0 of the undelayed signal output.

61

 AUXB1O Bit 1 of the auxiliary undelayed signal o/p

62

 B1OUT Bit 1 of the undelayed signal output.

63

 DO17 Bit 17 of the output bus.

66

 DO18 Bit 18 of the output bus.

67

 INTO Correlation period framing signal o/p

68

 SEO Shift Enable output.

69

 BLANKO Blanking Enable output

70

 DO19 Bit 19 of the output bus.

71

 DO20 Bit 20 of the output bus.
72 DO21 Bit 21 of the output bus.
75 DO22 Bit 22 of the output bus.
76 DO23 Bit 23 of the output bus.
77 DO24 Bit 24 of the output bus.
78 DO25 Bit 25 of the output bus.
81 DO26 Bit 26 of the output bus.
82 DO27 Bit 27 of the output bus
83 DO28 Bit 28 of the output bus.
84 DO29 Bit 29 of the output bus.

7,12,23,32,37,49,

54,65,74,79

 VDD Positive power supply. Normally +5V

6,13,24,31,48,

55,64,73,80

 VSS Supply reference. Ground.

 

6    Electrical Specifications

Reference is to Ground (VSS)

Absolute Maximum Ratings

Symbol Parameter Min. Max.

Units
Vdd Supply Boltage -0.3 5.5

V
Vi Voltage at Digital Inputs -0.3 Vdd+0.3

V
Ii Current into Digital Inputs -10 10

mA
Vo Voltage at Digital Outputs -0.3 Vdd+0.3

V
Io Current into Digital Outputs -10 10

mA
Tst Storage Temperature -55 110

oC
Tbias Temperature under bias -55 110

oC
P Power Dissipation

Watts

Recommended Operating Conditions

Symbol Characteristics Min. Max. Unit
Vdd Supply Voltage 4.5 5.5 V
Top Operating Temperature 0 70 oC
Vi Input Voltage 0 Vdd V
Idd Supply Current 8 mA/MHz

DC Electrical Characteristics

Symbol Characteristics Min. Max. Unit Test Conditions
Vih Input High Voltage 2.0 Vdd V
Vil Input Low Voltage Vss 0.8 V
Iil Input Leakage -10 10 µA
Voh Output High Voltage 2.4 Vdd V Ioh=0.4mA
Vol Output Low Voltage Vss 0.4 V Iol =3.2mA
Ioh Output High Current 0.4 mA Source Voh = 2.4V
Iol Output Low Current 3.2 mA Sink Vol = 0.4V
P Power Dissipation 4 W Outputs Unloaded

 

Electrical Specifications Cont.

AC Electrical Characteristics

Symbol

Parameter

Min.

Max.

Units

 Test Conditions
tck CLOCK Cycle Time

10

ns

 Note 1
tckr CLOCK Rise Time

1

ns

 Note 2
tckf CLOCK Fall Time

1

ns

 Note 3
tckw CLOCK Pulse Width

8

ns

 Note 1,4
tisu Data in Set Up

3.5

ns

 Note 5,8
tih Data in Hold

0

ns

 Note 6,8
tsd Data Out Delay

6.5

ns

 Note 7,9 CL = 30 pF
tck READ Cycle Time

50

ns

 Note 1
tckr READ Rise Time

4

ns

 Note 2
tckf READ Fall Time

4

ns

 Note 3
tckw READ Pulse Width

20

ns

 Note 1,4

Notes:

  1. Measured from valid Vil to valid Vil.
  2. Measured from valid Vil to valid Vih. 
  3. Measured from valid Vih to valid Vil.
  4. Measured from valid Vih to valid Vih.
  5. Measured from valid Vil or Vih to invalid Vil (rising CLOCK edge).
  6. Measured from valid Vih (rising CLOCK edge) to invalid Vih or Vil.
  7. Measured from valid Vih (rising CLOCK edge) to valid Voh or Vol.
  8. tisu and tih for CE are relative to the rising edge of READ.
  9. tsd for D0-D31 is relative to the rising edge of READ.

 

John Canaris
13 February 1995